The field of the invention relates to the fabrication of semiconductor devices and the resulting yield and reliability of fabricated semiconductor devices. More particularly, it relates to techniques for increasing the post-fabrication reliability of semiconductor wafers and devices disposed thereon.
The reliability of a semiconductor product can be described by a universal bathtub curve (FIG. 1), which plots the instantaneous failure rate as a function of time. The instantaneous failure rate may be generally defined as the ratio of (number of failures in dt)/dt and the population at time t. There are three parts in the universal curve. The first part is the rapid drop of instantaneous failure rate, which is called the extrinsic or early failure rate (EFR) or infant mortality rate of the chips when in machine use, mainly due to partial or latent electrical-defects. After the instantaneous failure rate drops, it reaches a steady state. Eventually the instantaneous failure rate increases, due to the intrinsic failure rate (IFR).
Early failure rate (EFR) of a particular semiconductor device depends on both the material properties and reliability (partial or latent) defect densities, and early failure typically happens within the first few months of operation under machine use conditions. Reliability defects are generally small partial defects that test good (i.e., do not result in faults) at the end of processing, t0, but cause early fails or infant mortality soon after introduction into the field service. Major reliability issues include interconnect electromigration, gate oxide breakdown, and hot carrier injection. For example, a partial open will reduce the line width in an interconnect, although the interconnect is still electrically connected. Current crowding and local heating in the interconnect with partial defects will promote accelerated electromigration and eventually cause voiding, that opens the line. These defects are called reliability or latent defects.
Since most microelectronics components have an infant mortality period of up to one year under ordinary operating conditions, the reliability problem in the infant mortality period becomes extremely important. Product is usually burnt-in to eliminate early failures in a short period of time (days) at accelerated stress conditions (high voltage and high temperature).
Burn-in of the integrated circuit (IC) modules eliminates the early fails or infant mortality devices, which are a major concern of semiconductor manufacturer as well as the Circuit Design groups or Fabless Companies. The burn-in test that subjects devices to higher than usual levels of stress, such as voltage and temperature, is a technique used to remove the chips with latent defects. One purpose for applying burn-in to IC products is to guarantee high reliability of the end products, by weeding out products that are susceptible to infant mortality from commercial application. However, the burn-in process tends to be very expensive. Applying accelerated stress conditions such as voltage, temperature, and the post-burn-in retest are associated with significant costs. Currently, burn-in costs around 5 billion dollars annually worldwide.
Accordingly, there is a need for efficiently and accurately predicting the early failure rates associated with IC products. That is, there is a need for cost-effective techniques for identifying IC product lots which are susceptible to infant mortality, so that the cost of Burn-In can be drastically reduced.
Accordingly, techniques and systems are provided for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.
In one embodiment, a method of determining whether to perform burn-in on a semiconductor product is disclosed. For the semiconductor product, a time to fail for one or more failure mechanisms is determined. For the semiconductor product, an instantaneous failure rate for the one or more failure mechanisms is also determined based on the determined time to fail for the one or more failure mechanisms and yield information obtained from the semiconductor product. A burn-in procedure is invoked on the semiconductor product when the determined instantaneous failure rate for such semiconductor product is not within a predetermined specification bound. In contrast, the burn-in procedure is skipped when the determined instantaneous failure rate for such semiconductor product is within the predetermined specification.
In a specific implementation, the determination of the instantaneous failure rate is based indirectly on the yield information and such determination includes (1) for the semiconductor product, determining the critical areas of the design data for each reliability early-failure mode, (2) inspecting one or more test structures on the semiconductor product to determine yield information (defect density, etc.,) for the semiconductor product lot immediately after the corresponding fabrication-process, (3) determining a reliability fault density for reliability defects in the semiconductor product based on the determined yield information and the determined critical area for reliability failure, and (4) for the semiconductor product, determining an instantaneous failure rate for the one or more failure mechanisms based on the determined time to failure for the one or more failure mechanisms.
In a further aspect, determining the critical area for reliability failure includes (1) determining a probability of failure function for yield of the semiconductor product, (2) providing a defect size distribution for the semiconductor product, (3) determining the critical area for yield for the semiconductor product based on the determined probability of failure function for yield and the defect size distribution for the semiconductor product, (4) determining a probability of failure function for yield plus reliability, (5) determining a critical area for yield plus reliability from the probability of failure function for yield-plus-reliability, and (6) determining the critical area for reliability by subtracting the critical area for yield from the critical area for yield plus reliability. In yet a further aspect, the determination of the probability of fail function for yield plus reliability comprises shifting the probability of fail curve for yield as a function of defect size to a minimum reliability defect size that will cause a reliability fault, but still testing good for yield.
In a specific embodiment, inspecting one or more test structures on the semiconductor product to determine yield information for the semiconductor product lot immediately after fabrication includes (1) inspecting the one or more test structures to determine test structure yield, (2) determining a log of test structure yield as a function of a size of the one or more test structures, and (3) determining a defect density, systematic yield, and alpha-curvature or the defect cluster parameter from the log of test structure yield as a function of the size.
In another aspect, the invention pertains to a computer program product for determining whether to perform burn-in on such semiconductor product. The computer program product includes at least one computer readable medium and computer program instructions stored within the at least one computer readable product operable to perform one or more of the above described methods.
In another embodiment, the invention pertains to a computer system for determining whether to perform burn-in on such semiconductor product. The computer system includes a processor and/or at least one memory operable to (1) for the semiconductor product, determine a time to fail for one or more failure mechanisms, (2) for the semiconductor product, determine an instantaneous failure rate for the one or more failure mechanisms based on the determined time to fail for the one or more failure mechanisms and yield information provided from inspection of such semiconductor product, (3) determine to perform a burn-in procedure on the semiconductor product when the determined instantaneous failure rate for such semiconductor product is not within a predetermined specification bound, and (4) determine to skip the burn-in procedure when the determined instantaneous failure rate for such semiconductor product is within the predetermined specification bound.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.